The present invention relates to a timing analysis apparatus, a timing analysis method, and a timing analysis program.
In common applications of an integrated circuit, a clock signal is generated by a clock source (root), and then the clock signal is fed therefrom to a clock supply destination device through a predetermined path.
Referring to FIG. 1, there is shown a schematic diagram of an example of an integrated circuit. The exemplary integrated circuit shown in FIG. 1 includes a plurality of drivers (I1 to I7) and a plurality of clock supply destination devices (a to d) (each of which is hereinafter referred to just as a clock supply destination wherever appropriate). The driver I1 is provided as a clock source for generating a clock signal. The drivers I2 and I3 are coupled at a stage subordinate to the clock source I1. At a stage subordinate to the driver I2, the drivers I4 and I5 are coupled. Likewise, at a stage subordinate to the driver I3, the drivers I6 and I7 are coupled. Further, the clock supply destination device a is coupled at a stage subordinate to the driver I4, the clock supply destination device b is coupled at a stage subordinate to the driver I5, the clock supply destination device c is coupled at a stage subordinate to the driver I6, and the clock supply destination device d is coupled at a stage subordinate to the driver I7.
In the integrated circuit shown in FIG. 1, the clock signal generated by the clock source I1 is fed therefrom to each clock supply destination device (a to d) through a predetermined path. For example, the clock signal is fed from the clock source I1 to the clock supply destination device a through the drivers I2 and I4.
It takes a certain period of time for the clock signal to reach each clock supply destination device. This period of time required for clock signal propagation to each clock supply destination device is referred to as a delay time. In a case where two paths are provided in an integrated circuit, a malfunction may occur therein if there is a significant difference in delay time between the two paths. The difference in delay time is referred to as clock skew. To prevent occurrence of a malfunction such as mentioned above in an integrated circuit, the degree of clock skew is estimated in design review thereof. Then, a margin is set up in circuit design according to the degree of clock skew estimated, and an operating frequency and other performance characteristics of the integrated circuit are determined based on the margin thus set up. Alternatively, the integrated circuit is redesigned according to the result of clock skew verification.
The degree of clock skew can be determined by calculating a value of difference in delay time between the two paths concerned. Where the two paths are branchingly provided via a branch point, a delay time length in clock signal propagation from the clock source concerned to the branch point is the same on the two paths. Hence, regarding each path, a delay time in clock signal propagation from the branch point to each clock supply destination is determined. Then, in comparison between the two paths, the difference in delay time in clock signal propagation posterior to the branch point is determined as a value representing the degree of clock skew between the two paths. More specifically, delay time calculation is performed based on such factors as path routing from the branch point to each clock supply destination and the number of drivers disposed between the branch point and each clock supply destination.
In Patent Document 1 (Japanese Unexamined Patent Publication No. 2005-100310), there is disclosed a conventional technique related to the present invention, i.e., a delay time calculation method for calculating a delay time on a path in an integrated circuit. According to the delay time calculation method disclosed in the Patent Document 1, the degree of relative variation in delay time between comparative paths is separated into systematic components and random components, and delay time calculation is carried out by using the systematic components and random components thus separated.